1. Field of the Invention
The present invention relates to semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device including a clock driver for supplying a clock signal to a clock network such as a clock mesh and a fish-bone. More particularly, the invention relates to a layout of clock drivers in a semiconductor integrated circuit device.
2. Description of the Background Art
A clock driver for supplying a clock signal to a clock network called, e.g., a clock mesh or a fish-bone in an LSI is required to have a large drive capability because such a clock network extends over the whole LSI, and have a large load capacitance of hundreds of picofarads. In accordance with increase in operation speed of the LSI (Large Scale Integrated Circuit), a clock frequency determining the operation speed of LSI has been increased above hundreds of megahertz to the order of gigahertz. For accurately performing operations in accordance with such an extremely short clock cycle, sever specifications are required with respect to rounding and skew of the clock signal (a severe ratio Tr/Tf of rising to falling times, and a skew value in the order of 100 ps). For satisfying the requirements for the clock signal, clock distribution scheme has been devised in various manners.
FIG. 17 schematically shows a whole structure of a fast LSI in the prior art. The fast LSI shown in FIG. 17 includes an instruction memory 100 including four memory blocks MB0-MB3, a predecoder 101a for predecoding instructions read from memory blocks MB0 and MB1 of instruction memory 100, a predecoder 101b for predecoding instructions read from memory blocks MB2 and MB3 of instruction memory 100, a decoder 102 for decoding the instructions predecoded by predecoders 101a and 101b, a data pass 109 for executing processing in accordance with the instructions decoded by decoder 102, an MU control circuit 103 for controlling an operation of a memory unit (MU) that is one of execution units, an IU control circuit 104 for controlling an operation of an instruction unit (IU) executing the instructions, a data memory 107 storing data, a variable-length coding/decoding circuit (VLC/VLD) 108 performing variable-length coding and variable-length decoding of the received data, a cyclic redundancy coding block (CRC) 106 detecting and correcting an error in the received data based on a cyclic redundant code, and a peripheral interface circuit 105 performing transmission of data to and from an external memory as well as input/output of signals from and to an external device.
Memory unit MU controls the transfer of data between the processing unit and peripheral circuit block 105.
This fast LSI further includes a phase locked loop circuit (PLL) 110 generating a clock signal, repeaters R0-R7 transferring the clock signal sent from PLL 110, and clock drivers C0-C6 receiving the clock signal transferred via repeaters R0-R7, to drive output nodes at high speed to perform fast transmission of the clock signal.
In this fast LSI, the clock signal generated from PLL 110 is once transferred to repeater R0 arranged in a central region, and then is transferred to repeaters R1 and R4 on the upper and lower sides of the central repeater R0. Repeaters R1 and R4 transmit the clock signal in the opposite directions. More specifically, repeater R1 transfers the clock signal to repeaters R2 and R3 arranged on its opposite sides, and repeater R4 transfers the clock signal to repeater R7 as well as repeaters R5 and R6 arranged on the side opposite to repeater R7. Repeater R7 also transfers the clock signal to clock drivers C4 and C6.
The clock signal is first transferred to the central portion, and then is distributed in all directions via the repeaters so that the clock signal is distributed through substantially equal transmission distance, intending to reduce a clock skew.
In this arrangement of clock drivers in the fast LSI shown in FIG. 17, the drive capabilities and positions of repeaters R0-R7 are selected to minimize the delay of the clock signal sent from PLL 110, so that the clock signal of a waveform having steep rising and falling is transmitted. Repeaters R0-R7 and clock drivers C0-C6 are dispersed on a chip, aiming to transfer fast clock signals without rounding its waveform and causing a skew.
FIG. 18 schematically shows another structure of a fast LSI in the prior art. In FIG. 18, a fast LSI 150 includes three operation (or arithmetic) blocks 150a, 150b and 150c arranged dispersedly, a clock driver 151 arranged between operation blocks 150a and 150b, and a clock driver 152 arranged between operation blocks 150a and 150b and operation block 150c. These clock drivers 151 and 152 are disposed in a T-shaped form. Operation blocks 150a-150c of fast LSI 150 are, e.g., floating-point arithmetic units (FPUs), respectively, and each execute floating-point arithmetic processing.
A gate array is disposed in a region including clock drivers 151 and 152, and arrangement of basic transistors in clock drivers 151 and 152 is performed in a master step. Drive capabilities of clock drivers 151 and 152 are adjusted by aluminum interconnection lines in a slice step. Thus, the drive capabilities of clock drivers 151 and 152 are adjusted in accordance with the structures of operation blocks 150a-150c, and optimized clock drivers can be achieved for implementing fast clock transfer.
In the fast LSIs shown in FIGS. 17 and 18, a position of a large region occupying about 3% of the whole LSI must be determined in advance for use by the clock drivers, in order to provide sufficiently large drive capabilities of clock drivers for reducing a clock skew. Particularly, in the case of the fast LSI shown in FIG. 18, the gate array can achieve the drive capability larger than a drive capability to be used actually, and an unnecessary large area is occupied. Therefore, the arrangement of the clock drivers lowers the flexibility of the floor plan of LSI, and increases a dead region which cannot be used. Therefore, the are increase exceeds the area increase which is required by the clock drivers, resulting in a problem that the chip area of fast LSI increases.
The positions of these clock drivers are fixedly determined so that inequality in length is present among interconnection lines of this clock network (due to increase in dead region), and ununiformed clock driving is present among the clock drives in the clock network. Thereby, the clock skew cannot be reduced sufficiently.
Accordingly, the fast LSIs shown in FIGS. 17 and 18 leave much room for improvement for reducing the clock skew on the clock network.
In the arrangements shown in FIGS. 17 and 18, if lay-out of the operation blocks and others is determined, arrangement of the clock drivers is fixed depending on the arrangement of the operation blocks. Therefore, there is no versatility in arrangement of the clock drivers.
An object of the invention is to provide a semiconductor integrated circuit device which allows easy adjustment of a drive capability without increasing an area.
Another object of the invention is to provide a semiconductor integrated circuit device having clock drivers with an optimum drive capability arranged regardless of internal circuit arrangement, to reduce a clock skew and noises of clock drivers.
A semiconductor integrated circuit device according to the invention has power supply interconnection lines arranged in a mesh form, and clock drivers are arranged covering all over a region under the power supply interconnection lines.
A clock driver formation region is arranged to overlap with a ring interconnection line and a meshed-shape interconnection line, which in turn are arranged over the whole surface on a semiconductor substrate region. Thus, the clock drivers can be arranged within the semiconductor substrate region without increasing an area occupied by the substrate. Since the clock drivers are disposed distributedly over the whole surface of the substrate, an optimum clock driver arrangement can be achieved by appropriately selecting the clock drivers in accordance with a layout of internal circuits.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.